1. Field of the Invention
The invention relates to the field of electronics. More particularly, the invention relates to an asynchronous computer architecture that does not rely on a central clock for timing and control of data processing operations.
2. Related Art
Several proposals are known for making asynchronous circuits that potentially relate to executing program instructions, as reflected in the documents listed below.
1. S. B. Furber, P. Day, J. D. Garside, N. C. Paver and J. V. Woods, AMULET1: A Micropipelined ARM, Department of Computer Science, The University, Oxford Road, Manchester, M13 9PL, UK, Undated. PA1 2. Mark Edward Dean, STRIP: A Self-Timed Risc Processor, Technical Report No. CSL-TR-92-543, Stanford University Computer Systems Laboratory, July 1992. PA1 3. Jens Sparso and Jorgen Staunstrup, Delay-Insensitive Multi-Ring Structures, Integration, the VLSI Journal 15, 1993. PA1 4. J. D. Garside, A CMOS VLSI Implementation of an Asynchronous ALU, Department of Computer Science, Manchester University, Oxford Road, Manchester, M13 9PL, UK, Undated. PA1 5. S. B. Furber, P. Day, J. D. Garside, N. C. Paver, S. Temple and J. V. Woods, The Design and Evaluation of an Asynchronous Microprocessor, Department of Computer Science, The University, Oxford Road, Manchester M13 9PL, England, Undated. PA1 6. Jens Sparso, Jorgen Staunstrup, Michael Dantzer-Sorensen, Design of Delay Insensitive Circuits Using Multi-Ring Structures, European Design Automation Conference, EURO-VHDL '92, 1992 IEEE 0-8186-2780, pp. 15-20, August 1992. PA1 7. David E. Mueller, Asynchronous Logics and Application to Information Processing, Switching Theory in Space Technology, Stanford University Press, pp. 289-297, 1963. PA1 8. J. Staunstrup and M. R. Greenstreet, Designing Delay Insensitive Circuits using "Synchronized Transitions", Elsevier Science Publishers B. V. (North-Holland), IFIP, 1990. PA1 9. Teresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, Vol. 8, No. 11, pp. 1185-1205, November 1989. PA1 10. Ivan E. Sutherland, MICROPIPELINES, Communications Of The Acm, Vol. 32, No. 6, PP. 720-738, June 1989.
Despite these proposals, the dominant processors commercially available today are based on boolean clocked logic, and have centrally controlled architectures optimized for characteristics of boolean clocked logic.